DFT Design Engineer (SoC/ASIC)

TL;DR

DFT Design Engineer (SoC/ASIC): Implementing Design for Test (DFT) strategies for SoC/ASIC digital designs with an accent on scan chain insertion, MBIST, and ATPG. Focus on optimizing fault coverage, debugging Verilog testbenches, and ensuring system reliability through systematic quality metrics.

Location: Austin, US. US citizenship Required

Company

hirify.global is a leading provider of electronic design automation (EDA) software and hardware tools.

What you will do

• Implement scan chain insertion, compression scan technologies, and LBIST.
• Develop and execute memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) flows.
• Analyze and debug simulation failures to improve overall fault coverage.
• Verify ATPG testbenches and conduct root cause analysis of simulation mis-compares.
• Collaborate with cross-functional teams including Architecture and Design to meet project goals.
• Apply working knowledge of JTAG 1149.1/6, IEEE1500, and IEEE1687 standards.

Requirements

• 2-10 years of professional experience in SoC/ASIC Digital Design with a focus on DFT.
• US citizenship Required.
• Intimate knowledge of DFT insertion flows and ATPG to achieve design test coverage goals.
• Experience with scan chain insertion, compression scan, and MBIST.
• Hands-on experience with Verilog testbenches and debugging.
• Ability to work independently and collaboratively in a fast-paced project environment.

Nice to have

• Prior experience with hirify.global tools and flows.
• Knowledge of timing analysis and equivalency checks.