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Senior Staff Design Verification Engineer (DDR/LPDDR/HBM)

134 390 - 201 300$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Staff Design Verification Engineer (DDR/LPDDR/HBM): Developing and executing verification plans for high-speed memory interfaces with an accent on UVM/SystemVerilog-based environments and protocol-level validation. Focus on achieving coverage closure, debugging complex ASIC/SoC issues, and ensuring compliance with JEDEC standards for data center and AI chips.

Location: Santa Clara, CA

Salary: $134,390 - $201,300 per annum

Company

A global semiconductor leader providing essential building blocks for data infrastructure across cloud, AI, and carrier architectures.

What you will do

  • Develop and execute verification plans for high-speed memory interfaces, including DDR4/DDR5, LPDDR4/LPDDR5, and HBM2/HBM3.
  • Build and enhance UVM/SystemVerilog-based verification environments.
  • Create test benches, sequences, and checkers for functional and performance validation.
  • Perform protocol-level verification for memory controllers and PHY interfaces.
  • Analyze and debug simulation failures, identify root causes, and drive resolution.
  • Contribute to coverage-driven verification (CDV) across functional, code, and assertion coverage.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5-10 years of experience in ASIC/SoC verification.
  • Strong knowledge of DDR, LPDDR, or HBM protocols and architecture.
  • Expertise in SystemVerilog and UVM methodology.
  • Experience debugging complex verification issues using industry-standard simulation and waveform tools.
  • Must be eligible to access export-controlled information as defined under applicable U.S. law.

Nice to have

  • Knowledge of JEDEC standards for DDR/LPDDR/HBM.
  • Experience with assertion-based verification (SVA) and low-power verification (UPF).
  • Exposure to emulation platforms such as Palladium or Veloce.
  • Scripting skills in Python, Perl, or Shell.
  • Support for emulation/FPGA validation and post-silicon bring-up.

Culture & Benefits

  • Employee stock purchase plan with a 2-year look back.
  • Comprehensive family support programs to help balance work and home life.
  • Robust mental and physical health resources.
  • Recognition and service awards to celebrate contributions and milestones.
  • Financial well-being programs and comprehensive benefits for all career stages.

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