Sr DFT Engineer (Semiconductor)

TL;DR

Sr DFT Engineer (Semiconductor): Designing and implementing Design for Test (DFT) architectures, including scan, MBIST, and ATPG, for complex SoC and block-level designs with an accent on verification and silicon bring-up. Focus on debugging DFT issues, generating test vectors, and optimizing coverage using industry-standard tools.

Location: Remote within the USA; must be able to travel to an Arrow Client office or the closest designated Arrow office as requested.

Company

hirify.global (via eInfochips) is a leading global provider of product engineering and semiconductor design services, operating as a Fortune 154 company.

What you will do

• Design and implement DFT, including scan, MBIST, ATPG, and post-silicon diagnosis at block and SoC levels.
• Verify test patterns utilizing gate-level simulations.
• Collaborate with Synthesis, STA, and physical design teams to debug and resolve DFT-related problems.
• Partner with test engineers to bring up test vectors on silicon and ensure successful testing.

Requirements

• Deep understanding of DFT industry standards: Scan, ATPG, JTAG, and MBIST.
• Proven experience developing DFT specifications and architectures for complex designs.
• Proficiency in Siemens-Tessent and Synopsys tools for DFT implementation and vector generation.
• Strong TCL scripting skills for automating tasks and developing custom flows.
• Must be based in the United States and capable of traveling to office locations upon request.

Culture & Benefits

• Comprehensive Medical, Dental, and Vision insurance.
• 401k plan with matching contributions.
• HSA/HRA options and disability insurance.
• Generous Paid Time Off (vacation, sick, and holiday leave).
• Tuition reimbursement and professional growth opportunities.