Logic Design Intern (Embedded)

TL;DR

Logic Design Intern (Embedded): Contributing to the development of industry-leading DDR PHY designs with an accent on RTL development and quality assurance. Focus on implementing new features, performing design exercises, and collaborating with verification and structural design teams to ensure IP compliance and performance.

Location: Must be based in Penang, Malaysia (Hybrid work model)

Company

hirify.global is a global leader in semiconductor technology, building scalable engineering solutions and world-changing hardware.

What you will do

• Develop and implement internal IP RTL designs.
• Integrate new features and change requests into existing IP.
• Define power intent strategies and manage signal crossing for power planes and clock domains.
• Collaborate with verification and structural design teams for functional and physical implementation.
• Perform quality checks including RTL static analysis, timing/power convergence, and formal equivalent verification.

Requirements

• Bachelor or Master Degree in Electrical and Electronic or Computer Science Engineering.
• Proficiency in RTL design using Verilog or System Verilog.
• Knowledge of IP/Subsystem architecture and high-speed bus protocols.
• Familiarity with industry-standard FE/RTL design methodologies.
• Commitment to a minimum 3-month internship.

Culture & Benefits

• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work on cutting-edge process technologies and world-changing hardware.
• Exposure to industry-leading design methodologies and tools.
• Collaborative environment within the Central Engineering Group.