Senior RTL Engineer (Interconnect Design)

TL;DR

Senior RTL Engineer (Interconnect Design): Own microarchitecture and RTL implementation of scalable on-chip and off-chip interconnect components for a custom AI accelerator platform with an accent on NoC/coherent fabric design, verification closure, and performance optimization. Focus on driving design from requirements through tape-out and silicon bring-up while providing technical leadership across architecture, verification, and physical design.

Location: San Francisco, CA (hybrid: 3 days in the office per week). Relocation assistance offered.

Salary: $225K–$445K + offers equity

Company

OpenAI builds AI research and deployment systems, including next-generation hardware for large-scale training and inference.

What you will do

• Own microarchitecture, RTL design, and delivery of major SoC interconnect components (NoC fabrics, switches/routers/bridges, protocol adapters, arbiters, traffic-management logic, and off-chip interfaces).
• Perform substantial direct microarchitecture and RTL coding work for production-quality, parameterized SystemVerilog/Verilog.
• Drive third-party engagements to develop novel networking/interface protocols and silicon IP while maintaining design integrity.
• Analyze traffic patterns and optimize interconnect behavior under realistic workloads with performance and architecture teams.
• Collaborate on verification strategy (coverage plans, assertions, stress scenarios, and debug approaches) for highly concurrent fabric behavior.
• Partner with physical design to ensure implementability at target frequency/power/area (floorplan-aware design, pipeline strategy, timing closure, congestion management) and lead design reviews/mentoring.

Requirements

• Extensive experience designing and delivering complex SoC interconnect solutions (NoC, coherent fabric, memory subsystem, cache-coherent, or chip-level integration).
• Proven track record owning major RTL blocks or SoC subsystems from microarchitecture through tape-out and silicon bring-up.
• Deep expertise in Verilog/SystemVerilog and building clean, parameterized, production-quality RTL.
• Strong interconnect fundamentals: topology/routing, arbitration, virtual channels, flow control, buffering, ordering, QoS, coherency, deadlock avoidance, congestion management, and performance monitoring.
• Experience with common on-chip/chip-to-chip protocols and interfaces such as AXI, APB, CXL, PCIe, and Ethernet.
• Experience across RTL-adjacent signoff flows (lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, and design-for-test).

Nice to have

• Experience designing interconnect for AI accelerators/GPUs/CPUs, HPC systems, networking silicon, or large-scale datacenter silicon.
• Experience with memory consistency, virtualization/isolation, RAS, telemetry, or security requirements in complex SoCs.
• Experience with NoC performance modeling, traffic simulation/emulation, FPGA prototyping, or post-silicon performance analysis.
• Experience leading architecture or RTL delivery for first-generation silicon programs or rapidly evolving hardware platforms.

Culture & Benefits

• Hybrid work model: 3 days in the office per week.
• Relocation assistance for new employees.
• Senior, hands-on role with broad technical ownership across the silicon lifecycle.
• Mentoring and technical leadership opportunities across multiple engineering teams and external partners.

Hiring process

• Interviews focused on interconnect/RTL ownership, verification and signoff experience, and cross-team execution.
• Technical evaluation of microarchitecture/RTL coding depth and ability to drive performance and verification closure.