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обновлено 7 дней назад

Sr. Principal Software Engineer (DFT Hardware)

196 000 - 364 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Sr. Principal Software Engineer (DFT Hardware): Designing and implementing advanced Design-for-Test (DFT) hardware and on-chip test networks for next-generation SoCs with an accent on scan compression, hierarchical test access, and MBIST/LBIST. Focus on developing complex reusable IPs from architecture through delivery and driving high-coverage, low-cost test strategies.

Location: Austin, USA

Salary: $196,000–$364,000

Company

hirify.global Design Systems is a leading provider of electronic design automation (EDA) software and hardware for semiconductor and system design.

What you will do

  • Design and implement advanced DFT hardware, test fabrics, and on-chip test networks used in next-generation SoCs.
  • Develop industry-leading test solutions including scan compression, LBIST, MBIST, POST, and IST.
  • Manage the full-flow development of complex reusable IPs from architecture through final delivery.
  • Lead design, architecture, and microarchitecture reviews, ensuring implementation readiness.
  • Mentor senior and junior engineers and provide technical leadership across distributed development teams.
  • Collaborate with cross-functional teams to handle IP integrations, interface alignment, and quality checks.

Requirements

  • Strong background in Verilog/SystemVerilog RTL for digital hardware design and simulation.
  • Mastery of UVM and directed testbench IP verification, including test planning and coverage closure.
  • Experience with synthesis, lint, CDC/RDC, formal checks, and timing closure workflows.
  • Deep understanding of DFT requirements for SoCs, including IJTAG and test access architecture.
  • Proven ability to debug complex hardware issues across RTL, verification, and integration environments.
  • Strong project execution skills, including risk management and milestone ownership.

Nice to have

  • Experience with ISO 26262 functional safety concepts and ASIL-oriented design flows.
  • Exposure to security-aware hardware design, including secure boot and access control.
  • Experience in automotive, industrial, AI, or hyperscaler-class IP development.
  • Familiarity with hirify.global flows such as Xcelium, JasperGold, Genus, Innovus, Tempus, and Modus.

Culture & Benefits

  • Paid vacation and paid holidays.
  • 401(k) plan with employer match.
  • Employee stock purchase plan.
  • A variety of medical, dental, and vision plan options.

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