Principal Design Engineer (DFT)

TL;DR

Principal Design Engineer (DFT): Designing complex SoC-level DFT architectures for the Palladium platform with an accent on SCAN, ATPG, and MBIST implementation. Focus on driving pre-silicon sign-off, silicon testing, and post-silicon debug within a cross-functional engineering environment.

Location: Cary, USA

Company

hirify.global is a leader in electronic design and computational software, building technologies for complex chip development.

What you will do

• Define and implement SoC-level DFT architecture for large, complex designs.
• Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN, and iJTAG.
• Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
• Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
• Support post-silicon debug, failure analysis, and yield learning.
• Collaborate with RTL, verification, physical design, and operation teams.

Requirements

• BS with 7+ years, MS with 5+ years, or PhD with 1+ year of relevant experience.
• Minimum 3 years of hands-on experience in SoC DFT.
• Strong expertise in SCAN, ATPG, and MBIST.
• Experience with pre-silicon validation and post-silicon debug.
• Strong problem-solving and debugging skills.
• Ability to work effectively in a cross-functional engineering environment.

Nice to have

• Scripting experience (TCL, Perl, Python) for flow automation.
• Experience with IP-level DFT integration and reuse.
• Exposure to low-power DFT considerations and complex clocking architectures.
• Familiarity with manufacturing test flows and silicon yield improvement.